REVIEW - System Synthesis with VHDL


System Synthesis with VHDL


Petru Eles, Krzysztof Kuchcinski, Zebo Peng



Boom Koninklijke Uitgevers (1998)




Colin Paul Gloster


April 2004



This book is aimed at advanced students reading design automation, though I think that really the main thrust of the book is better suited to people starting a career in writing VHDL compilers. It is a bit hard to see who this book is really best for as anyone who would read it would already be familiar with much of what it says and would only get an overview of new areas. The introductory chapters take up nearly half of the book and are intended to be skipped if the reader already knows about their topics. Reading the chapters sequentially is slightly repetitive because later chapters recapitulate a little of what is in introductory chapters.

Much of the book is fairly theoretical without being impenetrable, so can serve well as a review of the some 200 referenced papers.

One surprising thing to note about the authors' technique is that they claim that a user's behavioural model is converted very early on into a structural version but they use extra steps to reduce the required number of gates (thereby yielding a space-efficient but slower solution). A lot of the book is actually about restructuring graphs for scheduling constraints and to reduce the gate count so could really be read by someone with no interest in programmable logic devices ... the Kernighan-Lin algorithm; linear programming; simulated annealing and othersare given varying degrees of coverage. Almost every problem discussed is NP-complete or NP.

One of their system level VHDL models is perhaps fairly small at 730 lines of code. Its code does not appear in the book. There is no substantial example of VHDL in the book: none is bigger than a page and most are less than half a page in length. The introductory chapter on VHDL is nice and covers more than enough of the language to understand what appears in the book. I found it convenient for contrasting VHDL93 (which they call VHDL'92) and VHDL87. VHDL is the input language for the authors' compiler, but they also survey system-level tools for other hardware description languages such as Cx and Verilog and HardwareC.

I learnt from the low-power synthesis chapter that two's complement is believed to consume more power than sign-magnitude due to the high level of switching needed if a variable/signal toggles between positive and negative often.

The final chapter often cites one reference that is missing from the bibliography.

Reading this book may be worthwhile, but you will not be able to work the way it advocates with ordinary tools so its impact on your work will be limited unless you decide to acquire an environment similar to those listed in the book. For some reason there is a chapter on testing which may encourage a design for testability culture ... but as with elsewhere in the book, it would be a good idea to check other texts for a practical way of implementing the notion.

Book cover image courtesy of Open Library.

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